Working with chip architecture team to define DFT specifications and define the chip test interface
Developing and implementing DFT architecture
Implementing DFT infrastructure
Working with the validation team to verify DFT implementations and implement design changes
Generating structural test vectors, analyzing and improving coverage
Working with designers on STA, physical, power and logical issues
Working with 3rd party IP’s vendor to integrate the provided design into the DFT infrastructure
Working with test engineers to bring up test vectors on Silicon
At least 5 years of DFT experience from VLSI companies - a must.
Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time.
Experience developing DFT specifications and driving DFT architecture and methods for designs
Knowledge of industry standards DFT and design tools.
Solid Understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon
Experience in debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG / 1500 related issues
Experience with STA constraints development and analysis for DFT modes and SDF simulations
Experienced in silicon bring-up, debug, and validation of DFT feature
Knowledge of Verilog and / or VHDL, and experience with simulators and waveform debugging tools.
Other locations :
Netanya, Israel, 1-2 travels per year may be required
BSEE is mandatory, MSEE - an advantage.