Formal Verification Engineer

IC Resources

London, South East, UK

1d ago

Formal Verification Engineer

Bristol, Cambridge, London, remote the choice is yours!

What a fantastic time to join my client, a company who have spent years creating graphics and AI chips that are at the core of our electronics products! Due to growth and new opportunities, they are expanding their IP portfolio into RISC-V CPUs.

This is a superb opportunity for a Formal Verification Engineer to join my client’s team. This group are a unique applied research team with a remit both to research and to deliver high performing hardware.

You will contribute to projects ranging from vector operations for CPUs, geometric calculations for real-time mobile graphics, to heavily optimised hardware for neural network and AI applications.

You will be joining a team with big ambitions and will play a key part in achieving them. As a Senior Formal Verification Engineer, you will be given challenging technical problems and be expected to help guide and shape the team moving forward.

With breadth and depth, this role offers a unique view of the company’s IP and the opportunity to become a subject specialist.

Responsibilities

Work with a team of mathematically focused engineers to verify optimal arithmetic hardware components.

Have the unique chance to contribute to cutting-edge CPU, GPU, and NNA products.

Design and implement formal verification strategies to achieve our design quality goals.

Write design properties in System Verilog and prove them using formal techniques.

Root-cause design issues in collaboration with other engineers.

Research new formal verification techniques and continuously drive the scope of what can be achieved with formal verification.

Utilise latest techniques, tools and technologies for verification activities.

Implement and maintain automated verification flows in languages such as Python / shell scripts.

I am looking for an Engineer with the following :

Expertise in digital integrated circuit formal verification techniques and methodologies.

Experience of IP or SOC level verification and know how to ensure quality for tape-out.

An ability to determine verification requirements from analysis of specifications.

Ability to phrase properties using formal languages, analyse falsified statements and develop methodologies to achieve convergence and property proofs.

Experience with System Verilog Assertions.

For more information contact Rachel Mason at IC Resources.

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