Senior Staff RF IC Design Engineer (PLL)

MediaTek

Cambourne

4d ago

Job Description

MediaTek is the world’s 4th largest global fabless semiconductor company, leading the market in chipset technology. Working together with 5G component suppliers and worldwide cellular operators around RF technology, MediaTek is quickly bringing a complete, standards-based and optimized 5G solution to the market.

Due to our continuing success and growth in the cellular chipset market, we have an exciting new opportunity in MediaTek’s UK RF IC Design Centre in Kent.

We are looking to recruit proven RF design talent, capable of delivering leading-edge products with demanding time to market requirements.

This is a great opportunity to be part of MediaTek’s highly experienced global RF team working on state-of-the-art 5G RF products in advanced CMOS processes.

Your responsibilities will include the specification, architecture design, circuit design, implementation and verification of synthesizer systems for 5G RF ICs.

Your focus will be on developing innovative synthesizer designs with leading edge performance and excellent results on first silicon.

Our UK RF Design Centre is located in West Malling, Kent with an additional team in Cambourne, Cambridgeshire. You will have the option to choose to work in either fantastic location.

MediaTek look for people with a great passion and work ethic, who have a broad set of technical skills and are ready to master new technologies and tackle some of industry’s greatest challenges to positively impact billions of future users.

From 4G and 5G smartphones, to tablets and digital television, MediaTek employees are changing the industry one innovative product after another.

Requirement Qualifications

MSc. or PhD in a closely related field

5 years relevant industrial experience

Proven track record of delivering high performance PLLs to mass production

Essential Technical Skills

Strong background in PLL design preferably for RF IC applications

Excellent understanding of state-of-the-art PLL architectures

Excellent understanding of PLL sub-blocks design such as VCOs / DCOs / PFD / TDC.

Experience with optimisation of RF or mixed-signal circuit layout

Experience with design in advanced CMOS technologies (28nm or below)

Strong analytical skills

A proven track record of delivering high performance products to mass production

Highly motivated to innovate to improve the performance of PLLs for next generation cellular Radios

Desirable Technical Skills

Experience with Cadence Analog Design Environment

Good understanding of RF performance requirements for cellular systems

Experience with EM simulation tools

Competent in doing data analysis and modelling using Matlab and / or Octave

Soft Skills

An innovative thinker with a passion and critical thinking mind for challenging technical problem solving

Highly motivated and results driven to see projects through to completion

A team player with the ability to work with others to complete challenging projects together as well as successfully working independently

A good communicator who is able to communicate effectively using a range of tools (Email, IM, VC etc.) with people across different timezones and cultures

Meticulous in ensuring work is completed to a high quality

Using skilled judgement to make decisions

Excellent time management and organisation skills

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