Design Verification Engineer (Pixel)
Apple
Cambridge, Cambridgeshire, United Kingdom
1d ago

Key Qualifications

  • You will have multiple years of relevant experience including :
  • Previous success owning DV for a complex block level
  • Expertise with a verification language such as SystemVerilog / UVM / OVM and / or strong software engineering (C / C++) skills
  • Expertise with Verilog / VHDL, HDL simulators, and waveform viewers
  • Experience defining coverage space, writing coverage model, analyzing results, complex constraints, writing complex TB components (BFMs, scoreboards and checkers etc.) and infrastructure
  • Pixel processing experience is a plus
  • Experience with Perl / Python, Shell scripting, Makefiles, TCL a plus
  • Excellent communication and interpersonal skills and ability to collaborate
  • Description

    You will have full responsibility for DV of a hardware block / IP, including leading a DV team and communicating plans and status to managementDevelop and track to verification plans on an aggressive schedule through sign-off, in coordination with design leads, architects, and program managementBuild and maintain verification test bench components and environmentsGenerate directed and directed random testsRun simulations and debug design and environment issuesCreate functional coverage points, analyze coverage, and improve test environment to target coverage holesCreate automated verification flows for block verificationApply knowledge of hardware description languages (VHDL / Verilog), verification languages (SystemVerilog / UVM / OVM), and simulators to verify complex designsWork with other block and core level engineers to ensure seamless verification flow

    Education & Experience

  • BS / MS CE or EE
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